Title: Professor
Department of Electronic Engineering, Shantou University
Key Laboratory of Intelligent Manufacturing Technology, Ministry of Education
Email: lylai@stu.edu.cn
Biography
Dr. Lai Liyang received his bachelor’s degree from Peking University, his master’s degree from the Institute of Microelectronics, Chinese Academy of Sciences, and his Ph.D. from the University of Illinois at Urbana-Champaign, USA.
His research focuses on design for test (DFT) of integrated circuits and electronic design automation (EDA).
After his doctoral studies, he worked for over ten years at Mentor Graphics, one of the world’s top three EDA companies. He possesses comprehensive industrial experience covering front-end to back-end design for DFT, as well as yield analysis. As a core R&D member, he participated in the development of EDA tools including ATPG, fault diagnosis, logic built-in self-test, and iJTAG. Relevant technologies have won numerous prestigious industrial awards: the IC Design Tools Award at DesignCon 2013 (the world’s leading IC industry conference), TSMC 28nm & 3D IC Reference Flow in 2011, and the Test-of-Time Award from Test & Measurement World in 2009. Multiple DFT solutions he led have been widely adopted in chip designs of global leading enterprises such as Intel, Broadcom, and Qualcomm.
He has published extensively in top-tier journals including IEEE TCAD and IEEE TVLSI, and flagship conferences such as ITC and VTS in the IC test field. He was awarded the Best Paper Award at ITC 2006 (CCF Class B conference, the premier international conference on semiconductor testing).
Following more than a decade of overseas study and career experience, he returned to academia and is dedicated to cultivating outstanding talents in the field of integrated circuit design for test. He has presided over 1 Major Research Plan Project of the National Natural Science Foundation of China, 1 General Project of Guangdong Provincial Natural Science Foundation, and 5 collaborative research projects with HiSilicon and Mentor Graphics (now Siemens). He was selected into the Guangdong Province Yangfan Program for Introducing Urgent High-level Talents in 2015.
He serves as a member of the STDF Memory Faillog Standard Committee, the Technical Committee on Fault Tolerant Computing, and the Technical Committee on Integrated Circuit Design of China Computer Federation (CCF).
He teaches fully English-taught core courses: Digital Circuit and Introduction to Computer System and Microcontroller. He adopts original international textbooks, with teaching contents and laboratory practices synchronized with world-renowned overseas universities. His courses have consistently ranked among the highest-rated courses by students of the Electronic Engineering Department for years. Under his supervision, students have won multiple competitions including the First Prize in 2023 OpenDACS Open-Source EDA and Chip Design Competition, Third Prize in the National Finals of 2024 China Robot and Artificial Intelligence Competition, and Second Prize in 2022 Guangdong Undergraduate Electronic Design Competition.
Research Interests
Electronic Design Automation (EDA industrial software), integrated circuit design for test (DFT), fault-tolerant computing.
Hosted Research Projects
Major Research Plan Project of National Natural Science Foundation of China, Design for Test Methods of Integrated Chips, No. 92473203, ongoing, Jan. 2025 – Dec. 2028, Principal Investigator
General Project of Guangdong Basic and Applied Basic Research Foundation, Research on Parallel Static Learning Algorithms for Heterogeneous Computing Architectures, No. 2022A1515011084, completed, Jan. 2022 – Dec. 2024, Principal Investigator
Open Project of State Key Laboratory of Computer Architecture, Institute of Computing Technology, CAS, Research on General-Purpose GPU Computing in Test Theory, No. CARCH201912, completed, Jan. 2020 – Dec. 2021, Principal Investigator
Guangdong Province Yangfan Program for Introducing Urgent High-level Talents, No. 140-14600602, completed, May 2016 – May 2019, Principal Investigator
Collaborative Project with Shenzhen HiSilicon Semiconductor Co., Ltd., No. 140-21222003, completed, Dec. 2021 – Dec. 2022, Principal Investigator
Collaborative Project with Huawei Technologies Co., Ltd., No. 140-21220018, completed, Jun. 2020 – Dec. 2021, Principal Investigator
Mentor Graphics (Siemens) Research Grant, No. 140-212350, completed, Jan. 2018 – Jan. 2019, Principal Investigator
Mentor Graphics (Siemens) Research Grant, No. 140-212312, completed, Dec. 2016 – Dec. 2017, Principal Investigator
Mentor Graphics (Siemens) Research Grant, No. 140-212284, completed, Dec. 2015 – Dec. 2016, Principal Investigator
Courses Taught
Published Monograph
Li Huawei, Zheng Wudong, Wen Xiaoqing, Lai Liyang, Ye Jing, Li Xiaowei. Testing of Digital Integrated Circuits: Theory, Methods and Practices. Tsinghua University Press, June 1, 2024. ISBN: 9787302662037.
Recent Publications
X. Lin, L. Lai, H. Li. Parallel Static Learning Toward Heterogeneous Computing Architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 43, no. 3, pp. 983–993, Mar. 2024. (SCI, CCF Class A)
J. Hu, G. Dai, L. Wang, L. Lai, Y. Huang, H. Yang, Y. Wang. Adaptive Multidimensional Parallel Fault Simulation Framework on Heterogeneous System. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 42, no. 6, pp. 1951–1964, Jun. 2023. (SCI, CCF Class A)
L. Lai, K.-H. Tsai, H. Li. GPGPU-Based ATPG System: Myth or Reality? IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 39, no. 1, pp. 239–247, Jan. 2020. (SCI, CCF Class A)
L. Lai, Z. Lin, Q. Wang. Sideway Scan, Solving the Achilles’ Heel of Scan-based Diagnosis. 2024 IEEE International Test Conference in Asia (ITC-Asia), Changsha, China, 2024, pp. 1–6. (EI, CCF Class C)
H. Liang, X. Lin, L. Lai, N. Wang, Y. Huang, F. Yang, Y. Yang. GPU-Based Concurrent Static Learning. 2023 IEEE International Test Conference (ITC), Anaheim, CA, USA, 2023, pp. 159–165. (EI, CCF Class B)
X. Lin, L. Lai, H. Li. Scalable Parallel Static Learning. 2021 IEEE International Test Conference in Asia (ITC-Asia), Shanghai, China, 2021, pp. 1–6. (EI, CCF Class C)
L. Lai, Q. Zhang, H. Tsai, W.-T. Cheng. GPU-based Hybrid Parallel Logic Simulation for Scan Patterns. 2020 IEEE International Test Conference in Asia (ITC-Asia), Taipei, China, 2020, pp. 118–123. (EI, CCF Class C)
Lai Liyang, Zheng Qianjun, Liang Haicheng, Li Huawei. High-Level Synthesis Design of Path Planning Algorithms. Journal of Electronics & Information Technology, vol. 46, no. 11, Nov. 2024, pp. 4132–4140. (EI)
Lai Liyang, Yang Yuxin, Li Huawei, Lin Xiaoze. Parallel Logic Simulation for Functional Vectors. Journal of Computer-Aided Design & Computer Graphics, vol. 35, no. 5, May 2023, pp. 803–810. (EI)
Lai Liyang, Li Huawei. Origin, Current Status, Applications and Impacts of Integrated Circuit Design for Test. CCF Communications of China Computer Federation, vol. 15, no. 5, May 2019, pp. 55–60.
Granted Patents
Lai Liyang, Wang Qitao, Lin Zefan, Huang Jiamin, Lin Wanting, You Jiaxin, Zheng Qianjun. Sideway Scan Circuit and Integrated Chip Based on Special Scan Chain Architecture. Patent No.: 2024109132419.
Lai Liyang, Lin Xiaoze, Liang Huaxiao, Liang Haicheng. Data Parallel-Based Static Learning Method and System for Digital Circuits. Patent No.: 202111063013X.
Lai Liyang, Lin Xiaoze, Liang Huaxiao, Liang Haicheng. Memory-Constrained Parallel Static Learning Method and System for Digital Circuits. Patent No.: 2021110644471.
L. Lai, Wu-Tung Cheng, Thomas Hans Rinderknecht. Built-In Self Test of Integrated Circuits Using Selectable Weighting of Test. U.S. Patent No. 7,840,865, Granted Nov. 23, 2010.
Ruifeng Guo, L. Lai, Yu Huang, Wu-Tung Cheng. Detection And Diagnosis Of Scan Cell Internal Defects. U.S. Patent No. 9,086,459, Granted Jul. 21, 2015.
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, L. Lai. Diagnosis Aware Scan Chain Stitching. U.S. Patent No. 9,015,543, Granted Apr. 21, 2015.
Yu Huang, Wu-Tung Cheng, Ting-Pu Tai, L. Lai, Ruifeng Guo. Compound Hold-Time Fault Diagnosis. U.S. Patent No. 8,862,956, Granted Oct. 14, 2014.
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Manish Sharma, L. Lai. Two-Dimensional Scan Architecture for Test Chips. U.S. Patent No. 9,222,978, Granted Dec. 29, 2015.
Wu-Tung Cheng, Ruifeng Guo, Yu Huang, L. Lai, Etienne Racine, Martin Kein, Ronald Press, Jing Ye, Yu Hu. Test Access Architecture for Stacked Memory and Logic Dies. Application No. 14/030,011, Sep. 18, 2013.
Wu-Tung Cheng, Ruifeng Guo, Yu Huang, L. Lai, Jing Ye, Yu Hu. Test architecture for characterizing interconnects in stacked designs. U.S. Patent No. 9,335,376, Granted Jun. 10, 2016.
